1. Field of the Invention
Example embodiments of the present invention relate generally to a semiconductor memory device, a local precharge circuit and method thereof, and more particularly to a semiconductor memory device, a local precharge circuit and method of performing a precharge operation.
2. Description of the Related Art
In a conventional semiconductor memory device, a bit line or local input/output line may be precharged to a precharge voltage level in order to reduce an occurrence of “floating” and to increase a sensing speed during a period when read and/or write operations are not actively performed. The precharge voltage level may be substantially the same as a bit line precharge voltage VBL, where the precharge voltage VBL may correspond to half of a power source voltage VINT or cell array operating voltage VINTA. The cell array operating voltage VINTA may be slightly less than or equal to the power source voltage VINT. The cell array operating voltage VINTA may be used to indicate a first logic level (e.g., a higher logic level or logic “1”) of data stored in a memory cell.
However, if a local sense amplifier is connected to a local input/output line and the local input/output line is precharged, different precharge voltage levels may be applied so as to increase a sensing speed of the local sense amplifier. Thus, if a local input/output line LIO, LIOB set to a voltage level VINTA, VSS is precharged to a first voltage level VBL, a noise source may be generated which may vary a voltage level of the first voltage level VBL based on the precharge operation of the local input/output line LIO, LIOB. The noise source may affect an operation of a first level VBL voltage generating circuit and may reduce a data sensing efficiency of the memory cell.
In order to compensate for the aforementioned noise source phenomenon, before a read or write operation to a memory cell begins (e.g., before an active mode is initiated), a precharge operation may be performed with a voltage set to the same level as a bit line precharge voltage. Then, a word line may be enabled and the active mode may be initiated, and the precharge operation may be performed with a voltage set to the same level as a cell array operating voltage VINTA. When the active mode completes, a precharge may again be performed with a voltage at the same level VBL as a bit line precharge voltage.
FIG. 1 illustrates a voltage level variation of a bit line and a local input/output line during a conventional precharge and data sensing operation.
Referring to FIG. 1, the local input/output line LIO, LIOB may be precharged to a first level VBL before an active mode is initiated. A word line WL connected to a memory cell may be enabled to read data of the memory cell, and the active mode may initiate. When the active mode is initiated, the local input/output line LIO, LIOB may be precharged to a second level VINTA. The precharge operation of the local input/output line LIO, LIOB to the second voltage level VINTA may continue until the word line is disabled and the active mode completes. However, while data is being transmitted to the local input/output line LIO, LIOB through bit line BL, BLB, the precharge of the local input/output line LIO, LIOB may not be performed. In other words, if a column address strobe (CAS) signal is applied and a column selection signal CSL is enabled such that column selection transistors connected between the bit line BL, BLB and the local input/output line LIO, LIOB are turned on, a precharge circuit for the local input/output line LIO, LIOB may not be operated. Voltage corresponding to data may be provided to the local input/output line, and the precharge enable signal may be disabled. After waiting for the active mode (e.g., a mode wherein data may be transmitted on the I/O line) to complete, the local input/output line LIO, LIOB may again be precharged to the first voltage level VBL.
A conventional semiconductor memory device performing the precharge operation described above will now be described in greater detail.
In the conventional semiconductor memory device, the local input/output line LIO, LIOB may be precharged to the second voltage level VINTA before the column selection signal CSL may be enabled in an active mode to perform a read operation. The column selection signal CSL may be enabled such that the bit line BL, BLB and the local input/output line LIO, LIOB may be electrically connected with each other. Thus, charge sharing may occur between the bit line BL, BLB and the local input/output line LIO, LIOB.
Because main local input/output line LIO and sub local input/output line LIOB are precharged to the second voltage level VINTA, voltage levels at the main bit line BL and the sub bit line BLB may increase via the above-described charge sharing, which may be indicated by reference number 30 of FIG. 1, which may thereby cause a data sensing error. For example, in reading data set to the first logic level (e.g., a higher logic level or logic “1”), a voltage level of the main bit line BL may be higher than a voltage level of the sub bit line BLB during normal operation, but if the voltage level of the main bit line BL increases via the charge sharing, the coupling may occur in a higher voltage level state of an adjacent bit line such that a voltage level of the sub bit line BLB may be higher than that of the main bit line BL. A local sense amplifier may thereby sense and amplify an inaccurate value, such that the output data may be inaccurate.
In a semiconductor memory device having a “long” tRCD condition, a delay may be provided until an RAS signal may be applied, and then a CAS signal may be applied, where the tRCD may be indicative of a delay time between receipt of the RAS and CAS signals. A column selection signal CSL may be enabled where a voltage level difference between the main bit line BL and the sub bit line BLB may be relatively large, which may reduce a probability of data failure. However, in a semiconductor memory device having a “short” tRCD condition, the column selection signal CSL may be enabled in a state where a voltage level difference between the main bit line BL and the sub bit line BLB is relatively low, thereby increasing the probability of a data failure (e.g., because noise may cause inaccurate data to be outputted).